Vhdl problems.

longhalloween · 05-10-2012 01:21PM #1

I'm trying to create a combinational logic encryption unit in VHDL and I can't figure out why it's not running.

My error report is:

** Error: E:/ProjectA/combinationalpartb.vhd(29): near " ' ": syntax error
** Error: E:/ProjectA/combinationalpartb.vhd(40): near " ' ": syntax error
** Error: E:/ProjectA/combinationalpartb.vhd(54): VHDL Compiler exiting

and my code is:

entity combinational is                                           --Define inputs and outputs
  port (input   :   in std_logic_vector(5 downto 0);
        output  :   out std_logic_vector(5 downto 0)
        );
  end combinational;
                                          

    architecture rtl of combinational is                                --Multiplexer Statement 
    
    signal data1,data2,output1,output2 : std_logic_vector(2 downto 0);
    
    begin                                     
    data1(2 downto 0) <= input(5 downto 3); 
    data2(2 downto 0) <= input(2 downto 0);                            
    
      with data1 select                                             --Multiplex first 3 bits.
      output1 <= '101' when '000',
                 '110' when '001',
                 '111' when '010',
                 '000' when '011',
                 '001' when '100',
                 '010' when '101',
                 '011' when '110',
                 '100' when '111';
                 
                
      with data2 select                                              --Multiplex second 3 bits.
      output2 <= '011' when '000',
                 '100' when '001',
                 '101' when '101',
                 '110' when '011',
                 '111' when '100',
                 '000' when '101',
                 '001' when '110',
                 '010' when '111';
                 
                
      
    output <= output1&output2;                                      -- Concatenate both outputs  
                
        
    end rtl;                                                        --End Combinational Logic

Any solution or pointers would be appreciated.

Procasinator · 05-10-2012 01:58PM

I don't know VHDL, but I believe your problem is you are using single quotes rather than double quotes in your when statements.

std_logic would be one bit (so '1' or '0' say), whereas you are using a std_logic_vector (so should be say "101" not '101').

Kind of like in many programming languages (C, C#, Java, etc) a character would be represented with single quotes (i.e. 'a') whereas a string would be with double quotes (i.e. "abc").

srsly78 · 05-10-2012 02:00PM

Show the code with line numbers. Which is line 29?

longhalloween · 05-10-2012 02:07PM

srsly78 wrote: »

Show the code with line numbers. Which is line 29?

Line 29 is "output 1 <=" and Line 40 is "output 2 <="

Seems I have the same problem at each point and I can't figure out what it is. I'll try the double quotes now, thanks!

longhalloween · 05-10-2012 02:14PM

Just got it there. The correct code is:

with data1 select                                             --Multiplex first 3 bits.
      output1 <= "101" when "000",
                 "110" when "001",
                 "111" when "010",
                 "000" when "011",
                 "001" when "100",
                 "010" when "101",
                 "011" when "110",
                 "100" when "111",
                 "000" when OTHERS;
                
      with data2 select                                              --Multiplex second 3 bits.
      output2 <= "011" when "000",
                 "100" when "001",
                 "101" when "010",
                 "110" when "011",
                 "111" when "100",
                 "000" when "101",
                 "001" when "110",
                 "010" when "111",
                 "000" when OTHERS;

Procasinator · 05-10-2012 02:15PM

You'll get the idea of the syntax here:
http://www.cs.sfu.ca/~ggbaker/reference/std_logic/1164/std_logic_vector.html

You see when assigning to std_logic_vector s, they use:
s2 <= "1100";

Where when only assigning to 1-bit of s (i.e. a std_logic), they use the single quotes:
s1(0) <= '0';

longhalloween · 05-10-2012 02:18PM

Thanks very much, I've never done any VHDL before 2 weeks ago so I'm in at the deep end.

Appreciate the help lads!

Vhdl problems.

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