Could someone help?

CerebralCortex

Would someone try get this vhdl code to do a sequence detect I can't get the focker to work thanks.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity state_mach is
Port ( din : in std_logic;
rst : in std_logic;
clk : in std_logic;
detect : out std_logic);
--link_dwn : out std_logic);
end state_mach;

architecture Behavioral of state_mach is
type states is(idle,s1,s2,s3,s4,s5,s6);
signal ns,cs:states:=idle; --default state is idle
begin
next_state: process(din,rst,clk) --next-state decode
begin

--if clk'event and clk='1' then
if rst='1' then
detect<='0';
ns<=idle;
else
case ns is
when idle=>
detect <='0';
if din='1' then
ns<=s1;
else ns<=idle;
end if;
when s1=>
detect <='0';
if din='0' then
ns<=s2;
else ns<=s1;
end if;
when s2=>
detect <='0';
if din='1' then
ns<=s2;
else ns<=idle;
end if;
when s3=>
detect <='0';
if din='1' then
ns<=s4;
else ns<=idle;
end if;
when s4=>
detect <='0';
if din='0' then
ns<=s5;
else ns<=s1;
end if;
when s5=>
detect <='0';
if din='1' then
ns<=s6;
else ns<=idle;
end if;
when s6=>
detect <='1';
if din='1' then
ns<=s1;
else ns<=idle;
end if;
--when others=>ns<=idle;
end case;
end if;
-- end if;
end process next_state;

syn_clk: process(clk) --synchronous process
begin
if(clk'event and clk = '1')then
cs<=ns;
end if;
end process syn_clk;
end Behavioral;

breadmonkey

you might be better off in the programming forum