how to calculate tag size of cache?

x in the city

hi lads

cant for the life of me figure out how the cache size of done here

theres a 16k tag of 16k x 8 and a 64k data cache of 16k x 32.

for a direct addressing memory of 32 bits. the total amount of memory is 16MBytes.

how is the 16k x 8 calculated for the tag bit anyone?

this is the memory with the byte enables on the lsb

23[tag--- 16|15----data |1|0|]0

ronivek

x in the city wrote: »

hi lads

cant for the life of me figure out how the cache size of done here

theres a 16k tag of 16k x 8 and a 64k data cache of 16k x 32.

for a direct addressing memory of 32 bits. the total amount of memory is 16MBytes.

how is the 16k x 8 calculated for the tag bit anyone?

this is the memory with the byte enables on the lsb

23[tag--- 16|15----data |1|0|]0

I honestly can't figure out what the question is here... 16k tag of 16k x 8? 64k data cache of 16k x 32? The total amount of what memory? Are you saying the least significant bit is a valid bit??

What type of cache are you dealing with here? Do you have an assignment or exam question you're trying to answer?

x in the city

ronivek wrote: »

I honestly can't figure out what the question is here... 16k tag of 16k x 8? 64k data cache of 16k x 32? The total amount of what memory? Are you saying the least significant bit is a valid bit??

What type of cache are you dealing with here? Do you have an assignment or exam question you're trying to answer?

Im wrecking my brains with this...!

grr, its an assignment and I was thinking I had it done, until I saw he wants byte addressable main memory.

this is what I have, im way confused with the byte addressable bit, and cant figure out the sizes of the cache/tag memories.



the question has a cache of 256kbytes, with a main memory of 256Meg (32 bits).

if byte addressing is used does that reduce the cache size?

ronivek

You have a 256KB cache sitting on front of a 256MB piece of memory.

Your 256KB cache is arranged in a particular way by virtue of the fact it is direct mapped and also as a result of the cache addressing scheme you've chosen.

Your index has a width of 14 bits which means you have 2^14 lines in your cache.

And your offset has a width of 4 bits; and as your word is defined as a byte each cache line is 16 bytes wide.

Your cache and main memory are inherently byte addressable due to the fact your word is defined as a byte and you're using a direct mapped cache; there's nothing you need to do to make it byte addressable.

Which part in particular are you struggling with?

x in the city

Thanks for the help, I am confused with the offset bit, another example I have seen has byte addressable memory also

and this is given for the physical address


[ 8 | 14 | 2 ]

for the tag, index and offset.

it says the memory is transferred in blocks of size 4 bytes each.

is that the same as what I am doing? (block size of 1 word or 4 bits).

so, Im confused whether the offset should be 2/4 bits I guess.

x in the city

ronivek:

does this look better? and the diagram, not sure on the size of the cache and tag s'ram IC's. is that correct?

ronivek

Ugh; my apologies.

I have no idea where my brain was last night when I wrote my post but it's completely arseways.

You have a 256KB cache sitting on front of 256MB main memory.

Your cache index is 14 bits wide; and as a result your cache contains 2^14 lines.

As your offset within each cache line is 4 bits wide; each cache line can contain 16 bytes of data with the offset selecting a single byte.

and this is given for the physical address


[ 8 | 14 | 2 ]

for the tag, index and offset.

it says the memory is transferred in blocks of size 4 bytes each.

is that the same as what I am doing? (block size of 1 word or 4 bits).

so, Im confused whether the offset should be 2/4 bits I guess.

Well that scheme would indicate a similar number of cache lines as above; i.e. 2^14; but the offset is indicating each cache line contains 4 bytes of data if the offset selects a single byte.

Depending on the implementation; your cache may place a full 4 bytes on the wire rather than a single byte.

Your diagram looks okay to me; but I only took a brief look and due to my poor information last night I'd take anything I say with a hefty pinch of salt!

x in the city

ronivek wrote: »

Ugh; my apologies.

I have no idea where my brain was last night when I wrote my post but it's completely arseways.

You have a 256KB cache sitting on front of 256MB main memory.

Your cache index is 14 bits wide; and as a result your cache contains 2^14 lines.

As your offset within each cache line is 4 bits wide; each cache line can contain 16 bytes of data with the offset selecting a single byte.




Well that scheme would indicate a similar number of cache lines as above; i.e. 2^14; but the offset is indicating each cache line contains 4 bytes of data if the offset selects a single byte.

Depending on the implementation; your cache may place a full 4 bytes on the wire rather than a single byte.

Your diagram looks okay to me; but I only took a brief look and due to my poor information last night I'd take anything I say with a hefty pinch of salt!

lol

no bother, i have done this out (again) and have attached my work, hopefully this is ok?

the last thing I have is the bit capacity and word length.

for a block of 4 bits we have

bit capacity = 2^16 + 272 = 65,808

word length = 16 + 256 = 272.

if our block is 8 bits, is this correct >

2^15 + 271 = 33,039 : bit capacity

15 + 256 : word length

sorry for all the questions, and happy new year.

* off topic, and not related to my work.

"Our cache size is 4KB = 212 bytes, with a line size of 16 bytes = 24 bytes. Therefore, our byte select field is 4 bits, our index field is 12-4 = 8 bits, which leaves 20 bits for our tag field. "

from this, how is 212 bytes related to a cache of 4Kb.?


my dog died today and feel like crap

ronivek

Where are these bit counts coming from exactly?

And you seem to be rather arbitrarily interchanging bit, byte and word; it's confusing!

Just to clarify; a byte is 8 bits and a word in this context is a byte.

I'm defining a block as a cache line; and a single cache line is 16 bytes wide. This makes each line 16 * 8 = 128 bits wide. As there are 2^14 cache lines(blocks) we have a total of 256KB which is (2^14 * (18 * 8)) bits.

Remember that 1KB(KibiByte) is (2^10 * 8) bits or 2^10 bytes.

I'm shattered so really not sure what the other stuff you're talking about relates to; sorry.

In terms of your diagrams they're looking pretty good; although your little offset diagram is a bit misleading in terms of the word select stuff; again have a look above and make sure you understand the definitions.

"Our cache size is 4KB = 212 bytes, with a line size of 16 bytes = 24 bytes. Therefore, our byte select field is 4 bits, our index field is 12-4 = 8 bits, which leaves 20 bits for our tag field. "

Buh. I randomly googled it and came up with your source and it still makes zero sense; 4KB is clearly =/= 212 bytes; and 16 bytes =/= 24 bytes. However; if you ignore the (= 212 bytes) and (= 24 bytes) you can see 4KB / 16 = 256. log (base 2) 256 gives you 8 so you know your index is 8 bits. Your cache line is 16 bytes and log (base 2) 16 gives you 4 so your offset is 4 bits and the remainder is your tag.

Sorry about your dog!

x in the city

think Im gonna leave my work done, I have another part on a 2 way assotiative memory. just sick of this for now.

should be ok. thanks for the help man.

PDelux

I'll throw my 2 cents in here..:)
For a 32-bit processor the cache line is usually 4 words which is 4x32-bits or 16 bytes wide(4x4x8-bit). A word is 32-bits on a 32-bit processor.
The reason there are 4 words on a cache line is because usually the data bus to memory is 128-bits wide and the CPU can read 128-bits in one go. So the CPU has 4 instruction words ready and waiting at any one time. This helps with the illusion of single cycle execution because in reality the cache is hiding the flash wait states. When the 128-bits are read from memory it may take 2 instruction cycles or more, but once the cache is ahead of this it keeps the illusion going.
Usually the 4 LSbs of the tag are not needed or assumed as 0 because each tag is associated with 4 32-bit words as said above. Remember the tag is just an address and in this case only needs to be on a 16-byte boundary. So this means the tag size is 4 times less than the data size. So in conclusion I believe this is why the tag size is 16KB and the data size is 64KB, i.e. four time larger.