l1 and l2 cache

eurotrotter

why are there 2 caches at all?
why is there not just one big cache that is equal to the sum of the 2 caches?
this has being annoying me for a while no
any ideas?
thanks
ed

trout

my understanding is that L1 cache is part of the CPU, on the same die, meaning the fastest possible access ... but this is expensive to manufacture and there are physical constraints to how big this cache can be. It is used for pipelining instructions and data to be operated on by the CPU

L2 cache is external to the CPU, and runs at higher speeds than normal RAM, but slower than L1 ... as L2 cache is dropped on-board there are fewer physical constraints ... but you get less bang for your buck

CPU's with larger L1 cache tend to be more powerful, and expensive.
CPU's with a bias towards L2 cache are cheaper to implement, but tend to be less powerful.

i guess it's all about choice

linkehs for more info
http://www.geek.com/glossary/glossary_search.cgi?l
http://www.karbosguide.com/books/pcarchitecture/chapter10.htm

Khannie

I thought L2 cache was on the same die also, just physically further from the registers. (edit: and not part of the CPU core).

No doubt about it though, it's based on cost per KB. L1 cache is ching ching ching, while L2 cache is only ching ching.

rogue-entity

The purpose of L1 and L2 cache is to act as a buffer between the CPU and the compartivly boards-like slow speed of the Ram. Typically RAM will operate at the Front Side Bus clock speed, say 800MHz, the CPU operates a few times faster then this (as determined by the clock multiplier which gives you the CPU clock speed).

The L1 and L2 cache (CPU cache) is located on the CPU and generally operates at the CPU clock speed, although L2 cache may operate at the Front Side Bus (and RAM) clock speed instead. The CPU cache stores the memory addresses and data most frequently accessed from the main ram, the purpose of which is to speed up accesses to the main memory and bring the memory latency closer to that of the Cache memory then the larger latency of the main ram which is slower.

Webmonkey

Yep and as far as i know reason they expensive to manufacture is because data is stored using flip flops and lots of them!
Ram and slower memory uses Capactors which need to be constantly recharged to keep information. Capacitors cheaper to manufacturer as well though i'm guessing this

Correct me if i'm wrong here beign a while since i've looked into these

trout

Webmonkey wrote:

Yep and as far as i know reason they expensive to manufacture is because data is stored using flip flops and lots of them!
Ram and slower memory uses Capactors which need to be constantly recharged to keep information. Capacitors cheaper to manufacturer as well though i'm guessing this

Correct me if i'm wrong here beign a while since i've looked into these

L1 & L2 cache uses SRAM (Static RAM) technology with access times in the order of 10 ns ... user RAM (ie not CPU cache) uses DRAM (Dynamic RAM) technology with access times in the order of 40+ ns

SRAM involves 4 or 6 transistors for each cell, DRAM usually has 1 transistor & 1 capacitor per cell ... the complex arrangement of transistors in SRAM and the static nature of the cell accounts for the higher manufacturing cost

L1 cache, very high speed & very high cost, serves the CPU data+instructions ... L2 cache, high speed and high cost, serves L1 cache

Khannie and rogue-entity are quite right .. L2 cache now tends to be on the CPU die ... older processors (pre Celeron and Athlon) the L2 cache was external to the processor ... i am not as up-to-date as i'd like to think ...oops:rolleyes:

Dempsey

rogue-entity wrote:

The purpose of L1 and L2 cache is to act as a buffer between the CPU and the compartivly boards-like slow speed of the Ram. Typically RAM will operate at the Front Side Bus clock speed, say 800MHz, the CPU operates a few times faster then this (as determined by the clock multiplier which gives you the CPU clock speed).

The L1 and L2 cache (CPU cache) is located on the CPU and generally operates at the CPU clock speed, although L2 cache may operate at the Front Side Bus (and RAM) clock speed instead. The CPU cache stores the memory addresses and data most frequently accessed from the main ram, the purpose of which is to speed up accesses to the main memory and bring the memory latency closer to that of the Cache memory then the larger latency of the main ram which is slower.

Nail on head

Anti

Btw L2 cache has the bigger boost in performance. especially multimedia.

Sully

rogue-entity wrote:

The purpose of L1 and L2 cache is to act as a buffer between the CPU and the compartivly boards-like slow speed of the Ram. Typically RAM will operate at the Front Side Bus clock speed, say 800MHz, the CPU operates a few times faster then this (as determined by the clock multiplier which gives you the CPU clock speed).

The L1 and L2 cache (CPU cache) is located on the CPU and generally operates at the CPU clock speed, although L2 cache may operate at the Front Side Bus (and RAM) clock speed instead. The CPU cache stores the memory addresses and data most frequently accessed from the main ram, the purpose of which is to speed up accesses to the main memory and bring the memory latency closer to that of the Cache memory then the larger latency of the main ram which is slower.

They actually teach you something inside in that college? :O

Dempsey

Yea, Ctrl + C & Ctrl + V, LOL

Webmonkey

No they teach it alright in Computer Architecture at least in my course.
Anyways, hmm sure SRAM made with transistors, - well obviously they there for switching purposes but always thought SRAM used DType Flip Flops?

Dempsey

SRAM is purely flip flops
DRAM is one transistor and a capacitor and uses a refresh circuit